1. Field of the Invention
The present invention relates to methods for electrically isolating dielectric materials. More particularly, the invention pertains to methods for electrical isolation, i.e., passivation of exposed silicon such as occurs on the back side of a semiconductor (SC) wafer comprising semiconductor devices or dice of a DRAM, SRAM, or other semiconductor die configuration. The invention also pertains to passivation of apparatus such as carrier substrates, interposer substrates for flip-chip packaging, conductive interconnects for test packages, and the like.
2. Background of Related Art
Silicon is a basic material from which a broad range of semiconductor devices is composed. Silicon is a semiconductor while its oxidation product, silicon dioxide, acts as a dielectric (insulating) material. Thus, silicon dioxide is one of the classical insulators used to electrically isolate silicon from conductive leads, specific functional devices in electronic apparatus, and the atmosphere. Other insulators that are used include a variety of organic and inorganic compounds.
The manufacture of semiconductor devices is performed by forming a plurality of the functional devices on a wafer and subsequently separating each semiconductor device by cutting along a pattern of saw lines crisscrossing the wafer. The various processes for forming a semiconductor device such as a DRAM or SRAM device may be generally characterized as including crystal growth, bare wafer formation, surface preparation, oxidation/nitridation, heat treatment, patterning, layer deposition, doping, metallization, and packaging. Typically, each of these processes includes several subprocesses.
Layer deposition is generally performed by one of several processes, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering, and electron-beam evaporation. In cases where the desired layer is to be an oxide of the base material, e.g., silicon dioxide, another common method includes the direct thermal oxidation of the existing silicon surface. Although the processes by which “growth” of a passivation layer on silicon by oxidizing the surface are highly developed, they have certain limitations. First, the rate of formation significantly slows as the layer thickness increases. Long times at high temperature are generally required to form thick layers, such as field oxides, surface passivation layers, and some masking oxide layers. Secondly, the growth rate is a function of wafer orientation. The <111> planes of a wafer have more silicon atoms than <100> planes, thus leading to faster formation of a SiO2 layer. In addition, other factors affecting growth rates include the types and concentrations of doping materials in the silicon and the presence of polysilicon or impurities. Differential oxidation causes the resulting SiO2 layer to have a stepped surface. It should be noted that the initial costs and operating costs of oxidation furnaces are high. Furthermore, a problem, which must be considered in thermal oxidation, is the formation of surface dislocations which may cause circuit problems.
Another consideration relating to oxide growth is the inability to adequately passivate the lateral walls of a small via hole (such as a laser-formed microvia) of a multilayer device prior to deposition of a conductive material (such as tungsten) into the via hole. Present passivation methods for insulating the lateral walls of such small-diameter holes tend to produce uneven coverage, sometimes leading to either short circuits between the conductive via and the semiconductor or excessive filling of the via hole.
In forming semiconductor devices, the electrically conductive bond pads on the active surface are grounded to the back side of the wafer. Unless neutralized by a passivation layer, the wafer back side has a net positive (+) charge.
Bond pad formation typically includes applying a copper or aluminum base, then coating the base with another material so that wire bonds or conductive structures, such as solder, may be secured to the bond pad.
In the case of bond pads to which bond wires are to be secured, copper is typically employed as the bond pad material. As copper forms a “slippery” oxide that is difficult to remove with a wire bonding capillary, nickel and gold adhesion layers are typically used. As copper alone will not initiate the adhesion of nickel thereto, a palladium “strike”, or seed layer, is typically formed prior to conducting an electroless nickel-plating process.
Efforts have been made to use more aggressive plating chemistries in order to speed the plating rate and create a higher density coating at lower cost. Such chemistries, e.g., palladium chloride in hydrochloric acid, greatly enhance the plating rate and plate density. However, unless the wafer back side is first passivated, copper pads which communicate with the silicon substrate (e.g., pads that communicate with active-device regions of transistors) and, thus, which may form a circuit directly through the silicon substrate, may be attacked by the plating chemistry and dissolve in as little as several minutes of exposure, resulting in damaged pads with performance anomalies. In addition, bath chemicals will be inordinately consumed. The use of sulfuric acid in the palladium electroless plating solution may curb such an attack of the bond pads to some extent, but does not completely resolve this problem. Once the palladium strike has been formed, nickel may be plated onto the copper and palladium by way of electroless deposition processes, then a gold layer may be formed by immersion plating processes.
Aluminum is typically used as the base metal for bond pads that will receive solder balls or other discrete conductive elements. As aluminum is not itself solderable, adhesion layers are typically deposited onto aluminum bond pads. Again, nickel is often used as such an adhesion layer. Nickel does not, however, adhere well to aluminum. A zincating process, usually “double zinc”, is typically used to facilitate adhesion of electrolessly deposited nickel to aluminum. If the back side of the silicon substrate upon which the bond pads are carried is not adequately passivated, the zincating process may etch the aluminum bond pads or deposit large zinc grains, which, in turn, adversely affects the subsequently deposited nickel layer.
Moreover, in forming adhesion layers on both copper and aluminum bond pads, if the back side of the silicon substrate is not sufficiently passivated, these nickel and gold layers may also be loosely deposited onto portions of the back side, which may result in the formation of particles in the plating baths, shortening the lives thereof and creating potential problems for downstream processes which are particle-sensitive, such as subsequent tape and probe processes.
In the current state of the art, the general approach is to continue to use the more benign electroless plating method despite its overall cost.
In an alternative approach, a back side coating such as a photoresist material is first applied to the wafer back side to cover the wafer's substrate material, e.g., silicon or germanium, and provide protection from a more aggressive plating chemistry. This method has further disadvantages in that the wafer is required to be removed from its work surface and inverted for resist application by a spin-on technique. Inversion and spin-on deposition require extra steps and equipment, are time consuming, and require forcibly clamped placement of the wafer's active surface on the flat surface of a vacuum hold-down tool, sometimes leading to physical damage to the semiconductor devices being formed on the wafer.
In U.S. Pat. No. 6,022,814 of Mikoshiba et al., a method for forming a silicon dioxide layer is presented which includes the spin-coating of a resin compound having an O—COOH·O, Si—O, or Si—N backbone. After application, the coated surface is heat-treated to set the resin, followed by heating at between 250° C. and the glass transition point (˜450–500° C.) for 3 to 4 hours to form silicon dioxide. This method for forming a silicon dioxide layer suffers from the spin-coating disadvantages listed above. In addition, it requires significant furnace exposure at elevated temperatures.
It is desired to have a semiconductor manufacturing method to plate bond pads to achieve uniform high-quality, high-density pads. It is further desired to have such bond pad formation without wafer inversion, while minimizing chemical usage, minimizing time consumption, and reducing the use of high-cost equipment. In addition, it is desired to have a method to produce such semiconductor devices at an optimally high yield.
In a paper of Antti J. Niskanen, published prior to November 2000 and entitled LIQUID PHASE DEPOSITION OF SILICON DIOXIDE, the author briefly summarizes tests to determine the possibility of liquid phase deposition of silicon dioxide. In a paper of Sampo Niskanen, dated November 2000 and titled DEVELOPMENT OF LIQUID PHASE DEPOSITION OF ZIRCONIUM OXIDE AND COMPARISON TO SILICON DIOXIDE, a summary is presented of tests comparing liquid phase depositions of zirconium dioxide and silicon dioxide to form thin films.